@Article{Bahl1974,
  author   = {L. Bahl and J. Cocke and F. Jelinek and J. Raviv},
  journal  = {IEEE Transactions on Information Theory (TIT)},
  title    = {Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)},
  year     = {1974},
  volume   = {20},
  number   = {2},
  pages    = {284-287},
  abstract = {The general problem of estimating the a posteriori probabilities of the states and transitions of a Markov source observed through a discrete memoryless channel is considered. The decoding of linear block and convolutional codes to minimize symbol error probability is shown to be a special case of this problem. An optimal decoding algorithm is derived.},
  keywords = {Convolutional codes;Decoding;Estimation;Linear codes;Markov processes},
  doi      = {10.1109/TIT.1974.1055186},
  ISSN     = {0018-9448},
  month    = mar,
}

@InProceedings{Cassagne2016a,
  author    = {A. Cassagne and T. Tonnellier and C. Leroux and B. {Le Gal} and O. Aumage and D. Barthou},
  title     = {Beyond {G}bps Turbo decoder on multi-core {CPUs}},
  booktitle = {International Symposium on Turbo Codes and Iterative Information Processing (ISTC)},
  year      = {2016},
  pages     = {136--140},
  month     = sep,
  publisher = {IEEE},
  abstract  = {This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K $<$; 4096.},
  doi       = {10.1109/ISTC.2016.7593092},
  file      = {:pdf/Cassagne2016a - Beyond Gbps Turbo Decoder on Multi-Core CPUs.pdf:PDF;:pdf/Cassagne2016a - Beyond Gbps Turbo Decoder on Multi-Core CPUs [poster].pdf:PDF},
  groups    = {Turbo Codes, Software Decoders, HoF Turbo - MAP, AFF3CT},
  keywords  = {codecs, maximum likelihood decoding, microprocessor chips, turbo codes, Gbps turbo decoder, energy efficiency, enhanced max-log-MAP turbo decoding variant, inter-frame SIMD strategy, multicore CPU, portable software turbo decoder, rate-l/3 LTE codes, Instruction sets, Measurement},
}

@InProceedings{Wu2013,
  author    = {M. Wu and G. Wang and B. Yin and C. Studer and J. R. Cavallaro},
  title     = {{HSPA+/LTE-A} Turbo Decoder on {GPU} and Multicore {CPU}},
  booktitle = {Asilomar Conference on Signals, Systems, and Computers (ACSSC)},
  year      = {2013},
  pages     = {824--828},
  month     = nov,
  publisher = {IEEE},
  abstract  = {This paper compares two implementations of reconfigurable and high-throughput turbo decoders. The first implementation is optimized for an NVIDIA Kepler graphics processing unit (GPU), whereas the second implementation is for an Intel Ivy Bridge processor. Both implementations support max-log-MAP and log-MAP turbo decoding algorithms, various code rates, different interleaver types, and all block-lengths, as specified by HSPA; and LTE-Advanced. In order to ensure a fair comparison between both implementations, we perform device-specific optimizations to improve the decoding throughput and error-rate performance. Our results show that the Intel Ivy Bridge processor implementation achieves up to 2$\times$ higher decoding throughput than our GPU implementation. In addition our CPU implementation requires roughly 4$\times$ fewer codewords to be processed in parallel to achieve its peak throughput.},
  doi       = {10.1109/ACSSC.2013.6810402},
  file      = {:pdf/Wu2013 - HSPA+ LTE-A Turbo Decoder on GPU and Multicore CPU.pdf:PDF},
  groups    = {Turbo Codes, Software Decoders, HoF Turbo - MAP},
  keywords  = {Long Term Evolution, graphics processing units, maximum likelihood decoding, multiprocessing systems, turbo codes, GPU, HSPA, Intel Ivy Bridge processor, LTE-Advanced, NVIDIA Kepler graphics processing unit, block-lengths, code rates, decoding throughput, device-specific optimizations, error-rate performance, high-throughput turbo decoders, interleaver types, log-MAP turbo decoding algorithms, max-log-MAP algorithms, multicore CPU, reconfigurable turbo decoders, Approximation methods, Decoding, Graphics processing units, Measurement, Throughput, Turbo codes, Vectors},
}